The FFT butterfly operation in 4 processor cycles on a 24 bit fixed-point DSP with a pipelined multiplier
نویسندگان
چکیده
Most of the existing Digital Signal Processors (DSPs) are optimized for a fast and e cient computation of the Fast Fourier Transform (FFT). However, there are only two oating-point DSPs available, which perform the butter y operation of a FFT in 4 processor cycles, but no xed-point DSP is designed that way. The new 24 bit xed-point DSP DAISY, which is able to execute the butter y in 4 cycles even using a two-stage pipelined multiplier, is described in this paper. With this pipelined multiplication it is possible to reduce the processor cycle time signi cantly.
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